Todd Austin
Todd Austin
Professor of Computer Science and Electrical Engineering, University of Michigan
Verified email at - Homepage
Cited by
Cited by
MiBench: A free, commercially representative embedded benchmark suite
MR Guthaus, JS Ringenberg, D Ernst, TM Austin, T Mudge, RB Brown
Proceedings of the fourth annual IEEE international workshop on workload†…, 2001
The SimpleScalar tool set, version 2.0
D Burger, TM Austin
ACM SIGARCH computer architecture news 25 (3), 13-25, 1997
Rechnerarchitektur: von der digitalen Logik zum Parallelrechner
AS Tanenbaum, T Austin
Pearson Deutschland GmbH, 2014
SimpleScalar: An infrastructure for computer system modeling
T Austin, E Larson, D Ernst
Computer 35 (2), 59-67, 2002
Razor: A low-power pipeline based on circuit-level timing speculation
D Ernst, NS Kim, S Das, S Pant, R Rao, T Pham, C Ziesler, D Blaauw, ...
Proceedings. 36th Annual IEEE/ACM International Symposium on†…, 2003
Leakage current: Moore's law meets static power
NS Kim, T Austin, D Baauw, T Mudge, K Flautner, JS Hu, MJ Irwin, ...
computer 36 (12), 68-75, 2003
A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor
SS Mukherjee, C Weaver, J Emer, SK Reinhardt, T Austin
Proceedings. 36th Annual IEEE/ACM International Symposium on†…, 2003
DIVA: A reliable substrate for deep submicron microarchitecture design
TM Austin
MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on†…, 1999
Evaluating future microprocessors: The simplescalar tool set
D Burger, TM Austin, S Bennett
University of Wisconsin-Madison Department of Computer Sciences, 1996
Efficient detection of all pointer and array access errors
TM Austin, SE Breach, GS Sohi
Proceedings of the ACM SIGPLAN 1994 conference on Programming Language†…, 1994
A self-tuning DVS processor using delay-error detection and correction
S Das, D Roberts, S Lee, S Pant, D Blaauw, T Austin, K Flautner, T Mudge
IEEE Journal of Solid-State Circuits 41 (4), 792-804, 2006
Razor: circuit-level correction of timing errors for low-power operation
D Ernst, S Das, S Lee, D Blaauw, T Austin, T Mudge, NS Kim, K Flautner
IEEE Micro 24 (6), 10-20, 2004
Cache-conscious data placement
B Calder, C Krintz, S John, T Austin
Proceedings of the eighth international conference on Architectural support†…, 1998
Reliable systems on unreliable fabrics
T Austin, V Bertacco, S Mahlke, Y Cao
IEEE Design & Test of Computers 25 (4), 322-332, 2008
A2: Analog malicious hardware
K Yang, M Hicks, Q Dong, T Austin, D Sylvester
2016 IEEE symposium on security and privacy (SP), 18-37, 2016
A 2.60 pJ/Inst subthreshold sensor processor for optimal energy efficiency
B Zhai, L Nazhandali, J Olson, A Reeves, M Minuth, R Helfand, S Pant, ...
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., 154-155, 2006
Dynamic dependency analysis of ordinary programs
TM Austin, GS Sohi
Proceedings of the 19th annual international symposium on Computer†…, 1992
BulletProof: A defect-tolerant CMP switch architecture
K Constantinides, S Plaza, J Blome, B Zhang, V Bertacco, S Mahlke, ...
The Twelfth International Symposium on High-Performance Computer†…, 2006
Energy-efficient subthreshold processor design
B Zhai, S Pant, L Nazhandali, S Hanson, J Olson, A Reeves, M Minuth, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (8†…, 2009
ANVIL: Software-based protection against next-generation rowhammer attacks
ZB Aweke, SF Yitbarek, R Qiao, R Das, M Hicks, Y Oren, T Austin
ACM SIGPLAN Notices 51 (4), 743-755, 2016
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