| Multiobjective microarchitectural floorplanning for 2-D and 3-D ICs M Healy, M Vittes, M Ekpanyapong, CS Ballapuram, SK Lim, HHS Lee, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 133 | 2006 |
| Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory MB Healy, K Athikulwongse, R Goel, MM Hossain, DH Kim, YJ Lee, ... IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010 | 101 | 2010 |
| Design and analysis of 3D-MAPS (3D massively parallel processor with stacked memory) DH Kim, K Athikulwongse, MB Healy, MM Hossain, M Jung, I Khorosh, ... IEEE Transactions on Computers 64 (1), 112-125, 2013 | 84 | 2013 |
| Encoding a magic state with beyond break-even fidelity RS Gupta, N Sundaresan, T Alexander, CJ Wood, ST Merkel, MB Healy, ... Nature 625 (7994), 259-263, 2024 | 74 | 2024 |
| Power delivery system architecture for many-tier 3D systems MB Healy, SK Lim 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC …, 2010 | 45 | 2010 |
| A study of stacking limit and scaling in 3D ICs: An interconnect perspective MB Healy, SK Lim 2009 59th Electronic Components and Technology Conference, 1213-1220, 2009 | 44 | 2009 |
| Attaché: Towards ideal memory compression by mitigating metadata bandwidth overheads S Hong, PJ Nair, B Abali, A Buyuktosunoglu, KH Kim, M Healy 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018 | 43 | 2018 |
| Distributed TSV topology for 3-D power-supply networks MB Healy, SK Lim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (11 …, 2011 | 43 | 2011 |
| 3D stacking of high-performance processors P Emma, A Buyuktosunoglu, M Healy, K Kailas, V Puente, R Yu, ... 2014 IEEE 20th International Symposium on High Performance Computer …, 2014 | 39 | 2014 |
| Power management of multi-core chips: Challenges and pitfalls P Bose, A Buyuktosunoglu, JA Darringer, MS Gupta, MB Healy, ... 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 977-982, 2012 | 36 | 2012 |
| Thermal-aware 3D microarchitectural floorplanning M Ekpanyapong, MB Healy, CS Ballapuram, SK Lim, HS Lee, GH Loh Georgia Institute of Technology, 2004 | 32 | 2004 |
| Serum ferritin in plateletpheresis and whole blood donors F Duggan, K O'Sullivan, JP Power, M Healy, WG Murphy Transfusion and Apheresis Science 55 (1), 159-163, 2016 | 31 | 2016 |
| Detecting a cryogenic attack on a memory device with embedded error correction MB Healy, HC Hunter, CA Kilmer, K Kim, WE Maule US Patent 9,940,457, 2018 | 28 | 2018 |
| Error monitoring of a memory device containing embedded error correction MB Healy, HC Hunter, CA Kilmer, K Kim, WE Maule US Patent 9,606,851, 2017 | 28 | 2017 |
| 3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits A Buyuktosunoglu, PG Emma, AM Hartstein, MB Healy, KK Kailas US Patent 8,799,710, 2014 | 26 | 2014 |
| Thermal optimization in multi-granularity multi-core floorplanning MB Healy, HHS Lee, GH Loh, SK Lim 2009 Asia and South Pacific Design Automation Conference, 43-48, 2009 | 26 | 2009 |
| Microarchitectural floorplanning under performance and thermal tradeoff M Healy, M Vittes, M Ekpanyapong, C Ballapuram, SK Lim, HHS Lee, ... Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 26 | 2006 |
| Touché: Towards ideal and efficient cache compression by mitigating tag area overheads S Hong, B Abali, A Buyuktosunoglu, MB Healy, PJ Nair Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 25 | 2019 |
| Three-dimensional processing system having multiple caches that can be partitioned, conjoined, and managed according to more than one set of rules and/or configurations A Buyuktosunoglu, PG Emma, AM Hartstein, MB Healy, KK Kailas US Patent 9,336,144, 2016 | 25 | 2016 |
| 5G Network Slicing for Mission-critical use cases M Roddy, T Truong, P Walsh, M Al Bado, Y Wu, M Healy, S Ahearne 2019 IEEE 2nd 5G World Forum (5GWF), 409-414, 2019 | 24 | 2019 |
Sung Kyu LimProfessor, Georgia Institute of TechnologyVerified email at ece.gatech.edu
