Joćo Canas Ferreira
Joćo Canas Ferreira
INESC TEC and University of Porto
Verified email at - Homepage
Cited by
Cited by
An FPGA implementation of a long short-term memory neural network
JC Ferreira, J Fonseca
2016 International Conference on ReConFigurable Computing and FPGAs …, 2016
Support for partial run-time reconfiguration of platform FPGAs
ML Silva, JC Ferreira
Journal of Systems Architecture 52 (12), 709-726, 2006
Control and observation of analog nodes in mixed-signal boards
JS Matos, AC Lećo, JC Ferreira
Proceedings of IEEE International Test Conference-(ITC), 323-331, 1993
A routing protocol for WSN based on the implementation of source routing for minimum cost forwarding method
F Derogarian, JC Ferreira, VG Tavares
Proc. SENSORCOMM, 85, 2011
Generation of partial FPGA configurations at run-time
ML Silva, JC Ferreira
2008 International Conference on Field Programmable Logic and Applications …, 2008
Transparent trace-based binary acceleration for reconfigurable HW/SW systems
J Bispo, N Paulino, JMP Cardoso, JC Ferreira
IEEE Transactions on Industrial Informatics 9 (3), 1625-1634, 2012
REFLECT: Rendering FPGAs to multi-core embedded computing
JMP Cardoso, PC Diniz, Z Petrov, K Bertels, M Hübner, H van Someren, ...
Reconfigurable Computing, 261-289, 2011
Run-time reconfiguration support for FPGAs with embedded CPUs: The hardware layer
JC Ferreira, MM Silva
19th IEEE International Parallel and Distributed Processing Symposium, 4 pp., 2005
Tool to support computer architecture teaching and learning
B Nova, JC Ferreira, A Araśjo
2013 1st International Conference of the Portuguese Society for Engineering …, 2013
A scalable array for cellular genetic algorithms: TSP as case study
PV dos Santos, JC Alves, JC Ferreira
2012 International Conference on Reconfigurable Computing and FPGAs, 1-6, 2012
From instruction traces to specialized reconfigurable arrays
J Bispo, N Paulino, JMP Cardoso, JC Ferreira
2011 International Conference on Reconfigurable Computing and FPGAs, 386-391, 2011
Transparent runtime migration of loop-based traces of processor instructions to reconfigurable processing units
J Bispo, N Paulino, JMP Cardoso, JC Ferreira
International Journal of Reconfigurable Computing 2013, 2013
A Wearable Sensor Network for Human Locomotion Data Capture.
A Zambrano, F Derogarian, R Dias, MJ Abreu, AP Catarino, AM Rocha, ...
pHealth, 216-223, 2012
FPGA-based rectification of stereo images
JGP Rodrigues, JC Ferreira
2010 Conference on Design and Architectures for Signal and Image Processing …, 2010
Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems
ML Silva, JC Ferreira
IET Computers & Digital Techniques 1 (5), 461-471, 2007
Generation of customized accelerators for loop pipelining of binary instruction traces
NMC Paulino, JC Ferreira, JMP Cardoso
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (1), 21-34, 2016
Reconfigurable FPGA-based FFT processor for cognitive radio applications
ML Ferreira, A Barahimi, JC Ferreira
International Symposium on Applied Reconfigurable Computing, 223-232, 2016
Transparent acceleration of program execution using reconfigurable hardware
N Paulino, JC Ferreira, J Bispo, JMP Cardoso
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
A framework for hardware cellular genetic algorithms: An application to spectrum allocation in cognitive radio
PV dos Santos, JC Alves, JC Ferreira
2013 23rd International Conference on Field programmable Logic and …, 2013
Parallel implementation on FPGA of support vector machines using stochastic gradient descent
FF Lopes, JC Ferreira, MAC Fernandes
Electronics 8 (6), 631, 2019
The system can't perform the operation now. Try again later.
Articles 1–20