| Performance modeling using monte carlo simulation R Srinivasan, J Cook, O Lubeck IEEE Computer Architecture Letters 5 (1), 38-41, 2006 | 28 | 2006 |
| Fast, accurate microarchitecture simulation using statistical phase detection R Srinivasan, J Cook, S Cooper IEEE International Symposium on Performance Analysis of Systems and Software …, 2005 | 28 | 2005 |
| Ultra-fast cpu performance prediction: Extending the monte carlo approach R Srinivasan, J Cook, O Lubeck 2006 18th International Symposium on Computer Architecture and High …, 2006 | 18 | 2006 |
| Implementation and performance modeling of deterministic particle transport (Sweep3D) on the IBM Cell/BE O Lubeck, M Lang, R Srinivasan, G Johnson Scientific Programming 17 (1-2), 199-208, 2009 | 15 | 2009 |
| Montesim: a monte carlo performance model for in-order microachitectures R Srinivasan, O Lubeck ACM SIGARCH Computer Architecture News 33 (5), 75-80, 2005 | 12 | 2005 |
| Extending the monte carlo processor modeling technique: Statistical performance models of the niagara 2 processor W Alkohlani, J Cook, R Srinivasan 2010 39th International Conference on Parallel Processing, 363-374, 2010 | 11 | 2010 |
| Compiler-directed functional unit shutdown for microarchitecture power optimization S Talli, R Srinivasan, J Cook 2007 IEEE International Performance, Computing, and Communications …, 2007 | 11 | 2007 |
| Techniques for accelerating microprocessor simulation BE RAMKUMAR SRINIVASAN New Mexico State University, 2004 | 5 | 2004 |
| An idealistic neuro-ppm branch predictor R Srinivasan, E Frachtenberg, O Lubeck, S Pakin, J Cook Journal of Instruction-Level Parallelism 9, 1-13, 2007 | 3 | 2007 |
| Fast, accurate micro-architecture simulation R Srinivasan, J Cook Proc. of the Applications for a Changing World, ITEA Modelling & Simulation …, 2003 | 2 | 2003 |
| Neuro-PPM Branch Prediction R Srinivasan, E Frachtenberg, O Lubeck, S Pakin, J Cook The Second Journal of Instruction-Level Parallelism Championship Branch …, 2006 | 1 | 2006 |
| Evaluating Instruction Reorderings and Transformations for Microarchitecture Power Reduction R Srinivasan, J Cook, L Eisen Proc. of the 6th Annual Austin CAS International Conference, 2005 | 1 | 2005 |
| Intrinsic data locality of modern scientific workloads S Ramanathan, R Srinivasan, J Cook 2003 IEEE International Conference on Communications (Cat. No. 03CH37441), 77-85, 2003 | 1 | 2003 |
| Cheetah/RtlGen: A Methodology for Efficient Processor Performance Validation R Srinivasan, CD Krieger, J Callister, RM Blumberg | | |
| Comprehensive Compiler-Directed Power Management J Cook, R Srinivasan | | |
| Exploiting Benchmark Patterns for Efficient Microarchitecture Simulation R Srinivasan, J Cook, S Stochaj A A 2, 3, 0 | | |
Michael K LangLos Alamos National LaboratoryVerified email at lanl.gov
