| Standby-power-free integrated circuits using MTJ-based VLSI computing T Hanyu, T Endoh, D Suzuki, H Koike, Y Ma, N Onizawa, M Natsui, ... Proceedings of the IEEE 104 (10), 1844-1863, 2016 | 132 | 2016 |
| Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an immediate-power-up field programmable gate array D Suzuki, M Natsui, S Ikeda, H Hasegawa, K Miura, J Hayakawa, T Endoh, ... 2009 Symposium on VLSI Circuits, 80-81, 2009 | 85 | 2009 |
| Nonvolatile logic-in-memory LSI using cycle-based power gating and its application to motion-vector prediction M Natsui, D Suzuki, N Sakimura, R Nebashi, Y Tsuji, A Morioka, ... IEEE Journal of Solid-State Circuits 50 (2), 476-489, 2014 | 72 | 2014 |
| Six-input lookup table circuit with 62% fewer transistors using nonvolatile logic-in-memory architecture with series/parallel-connected magnetic tunnel junctions D Suzuki, M Natsui, T Endoh, H Ohno, T Hanyu Journal of Applied Physics 111 (7), 2012 | 72 | 2012 |
| Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating M Natsui, D Suzuki, N Sakimura, R Nebashi, Y Tsuji, A Morioka, ... 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 70 | 2013 |
| Cost-efficient self-terminated write driver for spin-transfer-torque RAM and logic D Suzuki, M Natsui, A Mochizuki, T Hanyu IEEE Transactions on Magnetics 50 (11), 1-4, 2014 | 67 | 2014 |
| Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure D Suzuki, M Natsui, A Mochizuki, S Miura, H Honjo, H Sato, S Fukami, ... 2015 Symposium on VLSI Circuits (VLSI Circuits), C172-C173, 2015 | 53 | 2015 |
| A 47.14- 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications M Natsui, D Suzuki, A Tamakoshi, T Watanabe, H Honjo, H Koike, ... IEEE Journal of Solid-State Circuits 54 (11), 2991-3004, 2019 | 51 | 2019 |
| Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA D Suzuki, M Natsui, T Hanyu 2012 IEEE 55th International Midwest Symposium on Circuits and Systems …, 2012 | 31 | 2012 |
| Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm T Hanyu, D Suzuki, N Onizawa, S Matsunaga, M Natsui, A Mochizuki 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 27 | 2015 |
| Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications D Suzuki, M Natsui, A Mochizuki, S Miura, H Honjo, K Kinoshita, H Sato, ... IEICE Electronics Express 10 (23), 20130772-20130772, 2013 | 26 | 2013 |
| 12.1 An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14 μW Operation at 200MHz M Natsui, D Suzuki, A Tamakoshi, T Watanabe, H Honjo, H Koike, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 202-204, 2019 | 25 | 2019 |
| Magnetic-tunnel-junction based low-energy nonvolatile flip-flop using an area-efficient self-terminated write driver D Suzuki, T Hanyu Journal of Applied Physics 117 (17), 2015 | 25 | 2015 |
| A 71%-area-reduced six-input nonvolatile lookup-table circuit using a three-terminal magnetic-tunnel-junction-based single-ended structure D Suzuki, Y Lin, M Natsui, T Hanyu Japanese Journal of Applied Physics 52 (4S), 04CM04, 2013 | 23 | 2013 |
| Design of a compact nonvolatile four-input logic element using a magnetic tunnel junction and metal–oxide–semiconductor hybrid structure D Suzuki, M Natsui, T Endoh, H Ohno, T Hanyu Japanese journal of applied physics 51 (4S), 04DM02, 2012 | 18 | 2012 |
| A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure D Suzuki, N Sakimura, M Natsui, A Mochizuki, T Sugibayashi, T Endoh, ... IEICE Electronics Express 11 (13), 20140296-20140296, 2014 | 15 | 2014 |
| Design of an MTJ-based nonvolatile lookup table circuit using an energy-efficient single-ended logic-in-memory structure D Suzuki, T Hanyu 2015 IEEE 58th International Midwest Symposium on Circuits and Systems …, 2015 | 12 | 2015 |
| Design of a process-variation-aware nonvolatile MTJ-based lookup-table circuit D Suzuki, M Natsui, H Ohno, T Hanyu Proc. Int. Conf. Solid-State Devices Materials, 1146-1147, 2010 | 12 | 2010 |
| Challenge of MOS/MTJ-hybrid nonvolatile logic-in-memory architecture in dark-silicon era T Hanyu, D Suzuki, A Mochizuki, M Natsui, N Onizawa, T Sugibayashi, ... 2014 IEEE International Electron Devices Meeting, 28.2. 1-28.2. 3, 2014 | 11 | 2014 |
| Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting D Suzuki, T Hanyu Japanese Journal of Applied Physics 57 (4S), 04FE09, 2018 | 10 | 2018 |
