Vasilis F. Pavlidis
Vasilis F. Pavlidis
Computer Science and University of Manchester
Verified email at cs.man.ac.uk - Homepage
Title
Cited by
Cited by
Year
3-D topologies for networks-on-chip
VF Pavlidis, EG Friedman
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 15 (10 …, 2007
5072007
Three-dimensional integrated circuit design
VF Pavlidis, EG Friedman
Morgan Kaufmann Pub, 2009
357*2009
Three-dimensional integrated circuits
VF Pavlidis, EG Friedman
Burlington, MA: Morgan Kaufmann, 2009
352*2009
Performance analysis of 3-D monolithic integrated circuits
S Bobba, A Chakraborty, O Thomas, P Batude, VF Pavlidis, G De Micheli
2010 IEEE International 3D Systems Integration Conference (3DIC), 1-4, 2010
1252010
Interconnect-based design methodologies for three-dimensional integrated circuits
VF Pavlidis, EG Friedman
Proceedings of the IEEE 97 (1), 123-140, 2009
1242009
Clock distribution networks for 3-D integrated Circuits
VF Pavlidis, I Savidis, EG Friedman
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE, 651-654, 2008
722008
Clock distribution networks in 3-D integrated systems
VF Pavlidis, I Savidis, EG Friedman
IEEE Transactions on very large scale integration (VLSI) systems 19 (12 …, 2011
492011
Analytical heat transfer model for thermal through-silicon vias
H Xu, VF Pavlidis, G De Micheli
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, 1-6, 2011
402011
Interconnect delay minimization through interlayer via placement in 3-D ICs
VF Pavlidis, EG Friedman
Proceedings of the 15th ACM Great Lakes symposium on VLSI, 20-25, 2005
352005
Power distribution paths in 3-D ICS
VF Pavlidis, G De Micheli
Proceedings of the 19th ACM Great Lakes symposium on VLSI, 263-268, 2009
242009
A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
K Siozios, VF Pavlidis, D Soudris
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 5 (1), 4, 2012
232012
The combined effect of process variations and power supply noise on clock skew and jitter
H Xu, VF Pavlidis, W Burleson, G De Micheli
Quality Electronic Design (ISQED), 2012 13th International Symposium on, 320-327, 2012
172012
A software-supported methodology for designing high-performance 3D FPGA architectures
K Siozios, K Sotiriadis, VF Pavlidis, D Soudris
2007 IFIP International Conference on Very Large Scale Integration, 54-59, 2007
172007
Exploring alternative 3D FPGA architectures: design methodology and CAD tool support
K Siozios, K Sotiriadis, VF Pavlidis, D Soudris
Field Programmable Logic and Applications, 2007. FPL 2007. International …, 2007
172007
Effect of process variations in 3D global clock distribution networks
H Xu, VF Pavlidis, G De Micheli
ACM Journal on Emerging Technologies in Computing Systems (JETC) 8 (3), 20, 2012
162012
Via placement for minimum interconnect delay in three-dimensional (3D) circuits
VF Pavlidis, EG Friedman
2006 IEEE International Symposium on Circuits and Systems, 4 pp.-4590, 2006
152006
Bandwidth-to-area comparison of through silicon vias and inductive links for 3-D ICs
IA Papistas, VF Pavlidis
2015 European Conference on Circuit Theory and Design (ECCTD), 1-4, 2015
132015
Process-induced skew variation for scaled 2-D and 3-D ICs
H Xu, VF Pavlidis, G De Micheli
Proceedings of the 12th ACM/IEEE international workshop on System level …, 2010
132010
IC thermal analyzer for versatile 3-D structures using multigrid preconditioned Krylov methods
S Ladenheim, YC Chen, M Mihajlović, V Pavlidis
Computer-Aided Design (ICCAD), 2016 IEEE/ACM International Conference on, 1-8, 2016
122016
Timing uncertainty in 3-D clock trees due to process variations and power supply noise
H Xu, VF Pavlidis, X Tang, W Burleson, G De Micheli
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (12 …, 2013
122013
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