| VLSI placement parameter optimization using deep reinforcement learning A Agnesina, K Chang, SK Lim Proceedings of the 39th international conference on computer-aided design, 1-9, 2020 | 62 | 2020 |
| Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools K Chang, S Sinha, B Cline, R Southerland, M Doherty, G Yeric, SK Lim 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 57 | 2016 |
| Compact-2D: A physical design methodology to build commercial-quality face-to-face-bonded 3D ICs BW Ku, K Chang, SK Lim Proceedings of the 2018 International Symposium on Physical Design, 90-97, 2018 | 40 | 2018 |
| Design automation and testing of monolithic 3D ICs: Opportunities, challenges, and solutions K Chang, A Koneru, K Chakrabarty, SK Lim 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 805-810, 2017 | 40 | 2017 |
| Power benefit study of monolithic 3D IC at the 7nm technology node K Chang, K Acharya, S Sinha, B Cline, G Yeric, SK Lim 2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015 | 26 | 2015 |
| Mapping control intensive kernels onto coarse-grained reconfigurable array architecture K Chang, K Choi 2008 International SoC Design Conference 1, I-362-I-365, 2008 | 26 | 2008 |
| Memory-centered communication apparatus in a coarse grained reconfigurable array KY Choi, KW Chang, JK Paek US Patent 8,949,550, 2015 | 23 | 2015 |
| Compact-2D: A physical design methodology to build two-tier gate-level 3-D ICs BW Ku, K Chang, SK Lim IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 22 | 2019 |
| Match-making for Monolithic 3D IC: Finding the right technology node K Chang, S Sinha, B Cline, G Yeric, SK Lim Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 19 | 2016 |
| Pin-3D: A physical synthesis and post-layout optimization flow for heterogeneous monolithic 3D ICs SSK Pentapati, K Chang, V Gerousis, R Sengupta, SK Lim Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 17 | 2020 |
| Monolithic 3D IC design: Power, performance, and area impact at 7nm K Acharya, K Chang, BW Ku, S Panth, S Sinha, B Cline, G Yeric, SK Lim 2016 17th international symposium on quality electronic design (ISQED), 41-48, 2016 | 16 | 2016 |
| Pseudo-3D approaches for commercial-grade RTL-to-GDS tool flow targeting monolithic 3D ICs H Park, BW Ku, K Chang, DE Shim, SK Lim Proceedings of the 2020 International Symposium on Physical Design, 47-54, 2020 | 15 | 2020 |
| Impact and design guideline of monolithic 3-D IC at the 7-nm technology node K Chang, K Acharya, S Sinha, B Cline, G Yeric, SK Lim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (7 …, 2017 | 14 | 2017 |
| Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition K Chang, D Kadetotad, Y Cao, J Seo, SK Lim 2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017 | 13 | 2017 |
| Memory-centric communication architecture for reconfigurable computing K Chang, K Choi Reconfigurable Computing: Architectures, Tools and Applications: 6th …, 2010 | 12 | 2010 |
| System-level power delivery network analysis and optimization for monolithic 3-D ICs K Chang, S Das, S Sinha, B Cline, G Yeric, SK Lim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (4), 888-898, 2019 | 11 | 2019 |
| Method for generating three-dimensional integrated circuit design SP Sinha, K Chang, BT Cline, JR Ebbin Raney SOUTHERLAND US Patent 10,678,985, 2020 | 10 | 2020 |
| RTL-to-GDS tool flow and design-for-test solutions for monolithic 3D ICs H Park, K Chang, BW Ku, J Kim, E Lee, D Kim, A Chaudhuri, S Banerjee, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-4, 2019 | 10 | 2019 |
| Frequency and time domain analysis of power delivery network for monolithic 3D ICs K Chang, S Das, S Sinha, B Cline, G Yeric, SK Lim 2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017 | 10 | 2017 |
| Automatic mapping of control-intensive kernels onto coarse-grained reconfigurable array architecture with speculative execution G Lee, K Chang, K Choi 2010 IEEE International Symposium on Parallel & Distributed Processing …, 2010 | 9 | 2010 |
Sung Kyu LimProfessor, Georgia Institute of TechnologyVerified email at ece.gatech.edu
